1. Field of the Invention
The present invention is related generally to an apparatus for and a method of detecting a malfunction of a FIFO (first-in first-out) memory and, more particularly, to an apparatus for and a method of detecting a malfunction of a FIFO memory, which are capable of detecting a relative malfunction between a control counter and address designating elements employed for the FIFO memory.
2. Related Background Art
A FIFO memory has hitherto existed as a memory used for hardware which constitutes a communication network. This FIFO memory is employed in the case of taking a synchronism of the data when multiplexing the data in, e.g., data communications.
FIG. 11 illustrates a typical construction of the FIFO memory. Referring to FIG. 11, a FIFO memory circuit 101 comprises a memory 102, a write address counter 103 and a read address counter 104 both of which are connected to the memory 102. The FIFO memory circuit 101 also comprises a control counter 105 connected to both of the write address counter 103 and the read address counter 104.
This memory is composed of a multiplicity of micro memory areas to which addresses are respectively given. Then, when writing the data to the memory 102, the write address counter 103 designates the address of the micro memory area in the memory 102 while the data inputted via an input data line .phi.1 is written to the micro memory areas in the memory 102 of which address is designated. Similarly, when reading the data from the memory 102, the read address counter 104 designates the address, while the data stored in the micro memory area corresponding to this address to an output data line .PHI.2 is read out.
The two address counters 103 and 104 designate the addresses according to the same sequence, whereby first-in first-out can be attained. For instance, it is assumed that the memory 102 has n-pieces of micro memory areas, and addresses 0 through n-1 are given to the respective memory areas. The two address counters 103 and 104 go on changing locations of the address designation in a sequence of 0 through n-1 as circulated.
The write address counter 103 is driven by a clock CLK1 generated outwardly of the FIFO memory circuit 101. Similarly, the read address counter 104 is driven by a clock CLK2 generated outside the FIFO memory circuit 101. Further, the two address counters 103 and 104 perform count-up during the receiving of a count enabling signal from a control counter 105 but stop the count-up during the shutting off of the count enabling signals.
The control counter 105 is a counter added for managing operating statuses of the above two counters 103, 104 and for controlling these counters. That is, it is possible to indirectly grasp an occupied condition of the memory 102 by relatively checking present output values (addresses) of the two counters 103 and 104. For this reason, the control counter 105 constructed to perform the count-up each time the address designated by the write address counter 103 is changed and performs the count-down each time the address designated by the read address counter 104 is changed. As a result, it follows that a count value of the control counter 105 indicates the number of the micro memory areas holding unread data in the memory 102. Then, when the count value reaches its maximum value (corresponding to the number of the micro memory areas), the control counter 105 shuts off the write enabling signal to the write address counter 103 in order to inhibit a new data from being written to the memory 102. Reversely, when the count value comes to "0", the control counter 105 shuts off the enabling signal to the read address counter 104 in order to inhibit reading the data from the memory 102. Note that the control counter 105 is driven by a clock CLK0 generated outwardly of the FIFO memory 4 circuit 101.
Only a parity check has hitherto been conducted to check a malfunction of the thus constructed FIFO memory circuit 101. The parity check involves adding check bits termed parity bits beforehand to the data to be written in accordance with a fixed rule. Then, when reading the data from the memory, there is checked whether or not the data added with the parity bits still maintain this fixed rule. In consequence of this checking, if the above fixed rule is collapsed, it is recognized that the data are not correctly written or read. If the data are not correctly written or read, there is a high possibility in which the FIFO memory itself malfunctions. Hence, the occurrence of the malfunction of the FIFO memory can be presumed even by this parity check.
In the conventional parity check described above, however, what is directly detected is only an error of the data. Hence, the conventional parity check is not capable of surely detecting the malfunction of the FIFO memory circuit 101, especially the malfunctions of the address designating elements 103, 104 and the control counter 105 themselves.
That is, the clock CLK0 for driving the control counter 105 is formed outside the FIFO memory circuit 101. Then, the clock CLK0 is formed independently of other clocks CLK1 and CLK2; or, the clock CLK0 is common to the clock CLK1 but formed independently of the clock CLK2; or alternatively, the clock CLK0 is common to the clock CLK2 but formed independently of the clock CLK1.
Accordingly, the following condition is induced. The clock CLK1 is inputted to the write address counter 103, while the clock CLK0 is abruptly shut off, so that it is not inputted to the control counter 105. Under this condition, the address counter 103 changes the designation address and performs a new writing process, but, nevertheless, the control counter 105 can not take in the information. Further, there is caused a condition which follows. The clock CLK2 is inputted to the read address counter 104. However, the clock CLK0 is abruptly shut off, so that it is not inputted to the control counter 105. Under this condition, the address counter 104 changes the designation address and effects a new reading process, but, nevertheless, the control counter 105 can not take in the information. Hence, in these cases, it may happen that the actual number of the micro memory areas holding the unread data in the memory 102 is not coincident with the count value of the control counter 105.
Incidentally, the increment and decrement of the control counter 105 are cumulative. Therefore, once such a data take-in defect is caused, the count value thereof is not restored to its normal status at all, even if the control counter 105 resumes the operation after clock CLKO has been restored afterward to its normal status.
Then, if the FIFO memory circuit 101 continues the operation without recognizing that such a malfunction of the control counter 105 is produced, drawbacks may be caused, which is the lack or the double-reading of the data, and so on.
The occurrence of lack of data is a problem arising under such a condition that the write address counter 103 changes the designation address, but, nevertheless, the control counter 105 does not count up. That is, under this condition, a larger number of micro memory areas than the count value recognized by the control counter 105 hold the unread data in the memory 102. In this case, the reading process is inhibited when the count value of the control counter 105 comes to "0", and, therefore, the read address counter 104 becomes incapable of reading in spite of the fact that the unread data remain in the memory. Further, the control counter 105 does not stop enabling the writing process so far as the count value recognized by the counter 105 itself does not reach the maximum value. Accordingly, for example, there may exist a case where a further writing process is enabled even when all the micro memory areas in the memory 102, as a matter of fact, hold the unread data. In this case, the first-in (previously written) data is erased by overwriting and is thus lost. Moreover, the read address counter 104 is incapable of distinguishing whether or not the data to be actually read has undergone a first-in process merely by designating the address according to a simply determined sequence. Consequently, when the read of the data is carried out in this state, the read address counter 104 reads overwritten last-in data in advance as if it is the erased first-in data. Thereafter, it follows that the read address counter 104 reads data entering intermediately. Accordingly, the data sequence becomes random.
Further, the double-reading of the data is the problem arising under such a condition that the control counter 105 does not count down despite the fact that the read address counter 104 changes the designation address. Under this condition, the unread data in the memory 102 are held only by a smaller number of micro memory areas than the count value recognized by the control counter 105. Hence, the read address counter 104 actually designates the read addresses for all the unread data and then reads the data. Nevertheless, the control counter 105 does not inhibit the reading process on the assumption that the unread data still remain. Therefore, it follows that the read address counter 104 further designates the read addresses. The read address counter 104 can not, however, distinguish whether or not the data to be actually read has already been read. For this reason, it follows that the data which has been once read but not yet erased is read once again. Accordingly, in this case also, the data sequence becomes random.
There exits a problem in which the malfunction of the control counter 105 which induces a variety of troubles can not be detected by the conventionally practiced parity check.
Further, one of the address counters 1.03 and 104 malfunctions, and, if the sequence of address designation is mistakenly set, the same problems as the above-mentioned arise.